1. Field of the Invention
The present invention relates generally to semiconductor technologies. More particularly, the present invention relates to a dynamic random access memory (DRAM) cell and array with an embedded double-gate fin-FET, and a method for fabricating such DRAM cell structure.
2. Description of the Prior Art
Currently used dynamic random access memory (DRAM) devices comprise memory cells with one transistor and one storage capacitor in series. In order to obtain a sufficiently large read signal of the DRAM memory cell, the storage capacitor has to provide a sufficient storage capacitance. On account of the limited memory cell area, storage capacitors which utilize the third dimension are therefore used. One embodiment of a three-dimensional storage capacitor is the so-called stacked capacitor, which is arranged in a manner laterally adjoining a transistor, preferably essentially above the transistor, the inner capacitor electrode being conductively connected to the transistor.
As the areas of the memory cells become smaller and smaller on account of increasing miniaturization, retaining the current driver capability of the transistor poses an increasing problem. The shrinking of the cell areas and the resultant shrinking of the transistor dimensions mean that the transistor width of the planar junction transistors decreases. This in turn has the effect of reducing the current switched through from the transistor to the storage capacitor. One possibility of retaining the current driver capability of the planar transistor with a reduced transistor width consists in correspondingly scaling the gate oxide thickness or the doping profile of the source/drain regions and of the channel region. However, there is the problem of increased leakage currents when the gate oxide thickness is reduced or the doping concentrations are higher.
As an alternative to planar DRAM selection transistors, vertically arranged transistors are increasingly being discussed in order, in the case of selection transistors, too, additionally to be able to utilize the third dimension and obtain larger transistor widths. However, vertically embodied transistors are very complicated in terms of process engineering and can be fabricated only with difficulty, in particular with regard to the connection technique of the source/drain regions and of the gate electrodes of the transistor. Further, during the operations of switching the transistor on and off, the semiconductor substrate is also concomitantly charged at the same time, and the so-called floating body effect occurs, as a result of which the switching speed of the transistor is greatly impaired.
In particular in connection with logic circuits, new junction transistor concepts are developed which can achieve a higher current intensity relative to the transistor width in comparison with the conventionally planar transistors. One possible short-channel junction transistor concept is the so-called double gate transistor, in which the channel region between source and drain regions is encompassed by a gate electrode at least on two sides, whereby a high current driver capability can be achieved even in the case of very short channel lengths since an increased channel width results in comparison with conventional planar transistors. In this case, it is preferred for the double gate transistor to be designed as a so-called fin-FET or fin-type field effect transistor, in which the channel region is embodied in the form of a fin between the source and drain regions, the channel region being encompassed by the gate electrode at least at the two opposite sides.
One prior art double gate fin-FET with floating body issue is described in a published paper entitled “Highly Scalable Sub-50 nm Vertical Double Gate Trench DRAM Cell”, Schloesser, T. Manger, D. Weis, R. Slesazeck, S. Lau, F. Tegen, S. Sesterhenn, M. Muemmler, M. Nuetzel, J. Temmler, D. Kowalski, B. Scheler, U. Stavrev, M. Koehler, D., Memory Dev. Center, Infineon Technol., Dresden, Germany; Electron Devices Meeting, 2004.
However, the conventional DRAM device with double gate fin-FET have drawbacks including complexity of the manufacturing processes, floating body effect and insufficient source/drain contact area that leads to high contact/junction resistance and reduced performance.
Therefore, there is a strong need in this industry to provide an improved DRAM cell structure with a double gate fin-FET and DRAM cell array capable of eliminating the prior art problems, as well as a method for fabricating such DRAM cell structure and DRAM cell array. The fabrication method should be less complex and should be more litho friendly, which can alleviate the problems encountered in the conventional process.